Fabrication and assembly turnaround alone can be one to several weeks depending on board complexity and where it's built. A mistake that forces a second spin doesn't just cost the reorder — it costs that entire cycle again, usually right when a team is under the most schedule pressure to start firmware bring-up. The checks below are the ones that most often get missed on a first board.
Power architecture
- Decoupling capacitors placed close to every IC power pin, not just present somewhere on the net — trace length and via placement matter for high-frequency noise suppression
- Voltage regulator thermal and current margins checked against actual worst-case load, not just typical operating current
- Power sequencing verified for any IC with specific power-up/power-down ordering requirements (common with radios, memory, and multi-rail SoCs)
- Ground and power plane continuity — no accidental splits under high-current paths or return-path discontinuities under fast signal traces
Signal integrity and layout
- Differential pairs length-matched and routed with consistent spacing (USB, high-speed SPI, any differential interface)
- Crystal/oscillator traces kept short and away from noisy switching nets, with correct load capacitance for the chosen crystal
- Antenna keep-out zones respected per the module or chip vendor's reference layout — this is one of the most common causes of poor RF range on a first prototype, and a factor worth checking against the enclosure's RF impact as well, since a metal case can undo a clean antenna layout
- High-speed or sensitive analog traces routed away from switching regulators and digital clock lines — the same grounding and routing discipline that a sensor's analog front-end depends on
Component and footprint verification
- Footprints checked against the actual datasheet package variant — pin-1 orientation, pad pitch, and thermal pad dimensions, not just the part number
- Component availability and lead time confirmed before layout is finalized, not discovered at the ordering stage — the same consolidation logic covered in our notes on BOM cost optimization
- Test points added for key power rails, reset lines, and any debug/programming interface — trivial to add before fab, expensive to add after, and one of the core practices behind designing for test
Manufacturability (DFM) review
- Minimum trace/space and via sizes confirmed against the fab house's actual capabilities, not generic assumptions
- Silkscreen legibility for reference designators, especially on densely populated boards
- Panelization and tab placement reviewed if the board will be assembled in panels
- Solder mask and paste stencil apertures reviewed for fine-pitch parts, where default settings often need adjustment
Before the order goes in
A design-rule check (DRC) passing clean is necessary but not sufficient — DRC catches electrical and spacing violations, not architectural mistakes like a missing decoupling cap or a misrouted antenna feed. A manual review pass against a checklist like this one, ideally by someone who didn't do the original layout, catches a different class of error than automated tools do.
How we approach this
We run a structured DFM and layout review before any board goes to fab, treating the checklist as a floor, not a substitute for engineering judgment on the specific design. See our embedded hardware work for how this fits into schematic capture through bring-up, or our PCB design services page for the full checklist in one place.
Related reading: once a board revision has passed this checklist, our notes on hardware version control cover how to track exactly which revision and BOM configuration ended up in each shipped unit.
